1. Field of the Invention
The present invention relates to an operand fetch in a data processing system having an instruction pipeline, and more particularly to a data processing system adaptable to high speed processing of a transfer instruction for storing the content of a storage location specified by a second operand in an instruction to a storage location specified by a first operand in the instruction.
2. Description of the Prior Art
In a data processing system, a technique calld instruction pipeline has been adopted in order to attain a high speed execution of instructions. This technique is shown and described in the U.S. Pat. Nos. 3,840,861 and 4,149,244 and is well known in recent computer technology. It, therefore, need not be explained in detail herein. Briefly speaking, the instructions are executed through the steps of calculating an operand address (step D), translating the address and table-looking up a buffer storage (step A), reading out an operand (step L), carrying out an arithmetic operation (step E), transferring store data to a storage control unit (step P) and writing data into a storage (step W). The processor has hardware corresponding to the respective steps. In this system, while the step W for a given instruction is being executed in the hardware for executing the step W, the step P for the next instruction can be simultaneously executed in the hardware for executing the step P. Accordingly, six instructions may be executed simultaneously, but in different steps. The system in which a plurality of instructions can be parallelly executed is called a pipeline system. When a data transfer instruction is to be executed in a pipeline-type processor, the step for calculation of an operand address takes twice as long a time as the time required for the other steps, that is, it takes two cycles. As a result, the hardware for the other steps which require one cycle for operation are idling for the following one cycle. During this period, the hardware for the other steps show an operation rate or factor of only 50%. More specifically, a transfer instruction includes an operation field for specifying the transfer operation, an L-field for indicating a total number of bytes to be transferred, a first operand field and a second operand field. It instructs that those bytes which are one byte more in number than the number specified by the L-field are to be transferred from the storage address indicated by the second operand field to storage addresses starting from the address indicated by the first operand field. The first and second operand fields each have a base register allocation section and a displacement section, and the address is calculated by adding the content of an allocated base register to the displacement value. One cycle is needed for the address calculation of the first operand and another cycle is needed for the address calculation of the second operand. Eight bytes are transferred at a time. When a total of 32 bytes are to be transferred, the transfer operation must be repeated four times. For the second and subsequent transfers, the sequentially increasing addresses which are 8 higher, 16 higher and so on than the storage address specified by the instruction are also calculated. This calculation also takes one cycle for each of the first and second operand addresses. Accordingly, in the example shown above, the operation factor is 50% during the eight cycles. This means that the speed of the instruction execution decreases to one half during this period.